ArrayFoldIn development
AF-X1
Application-class RISC-V processing and AI acceleration on one radiation-tolerant chip.
An application-class RISC-V processor paired with the on-chip AI accelerator, sharing memory and interconnect on one radiation-tolerant chip.
Applications
Use it when a mission needs processing and AI acceleration in one radiation-tolerant part.
- Machine-vision payloads: camera in, classifications out over Ethernet
- Onboard image triage for Earth observation, sending less to the ground
- Star tracker and attitude sensor processing
- Autonomy for drones and other high-reliability platforms
At a glance
- Core
- RV32 · 100 MHz target
- AI throughput
- 80 GOPS class
- I/O
- Ethernet · camera · SD
- Autonomy
- Runs with CPU off
Specifications
Compute
- Processor
- RV32, multithreading planned
- Target clock
- 100 MHz
- AI engine
- On-chip accelerator, ~80 GOPS (projected)
- Fabric efficiency
- ~200 GOPS/W (compute fabric, projected)
- Autonomy
- AI pipeline runs with the processor powered down
Figures are design targets until silicon is characterized.
Two engines, one part.
A processor for control, an accelerator for the math. Either one runs without the other.
Memory
- On-chip SRAM
- ECC-protected with hardware scrubbing
- External RAM
- Octal PSRAM, multi-device
- Boot flash
- xSPI, dual chip-select, A/B redundant images
Protected on-chip, expandable off.
Every on-chip bit is error-corrected. Capacity grows off-chip when the payload needs it.
Network & video
- Ethernet
- 10/100 RMII with a zero-CPU egress path
- Clustering
- Multi-chip sync + Ethernet ingress configuration
- Camera
- Parallel DVP / BT.656 video input with DMA
Camera in, decisions out.
The full pipeline runs over Ethernet with the processor asleep.
Storage & buses
- SD card
- Bulk storage for logging and payload data
- Spacecraft buses
- SpaceWire · CAN
- Serial
- 2× UART (always-live console) · SPI · I²C
- Control I/O
- Timers, watchdog, PWM, quadrature
Wired for the spacecraft.
SD for storage, SpaceWire and CAN for the bus, serial for everything else.
Flexible I/O
- AFPIO
- Deterministic programmable I/O engine
- Candidate applications
- MIL-STD-1553, USB full-speed
- Pin multiplexing
- Every pin muxed; validated whole-chip configurations
Interfaces in software.
If what you need isn't listed, AFPIO can usually build it without new silicon.
Package
- User I/O
- 44 pads
- Package
- 64-pin QFN, 9 × 9 mm
Temperature
| Parameter | Min | Typ | Max | Unit |
|---|---|---|---|---|
| Operating (target) | -40 | 25 | 125 | °C |
Targets; characterization follows first silicon.
Radiation
Radiation tolerance by architecture.
AF-X1 uses triple modular redundancy on critical logic, ECC-protected memory, and memory scrubbing.
TID and single-event test results will be published here as characterization completes.
Technical detail
Autonomous operation
- Cold-starts with the processor held off: the boot sequencer loads and starts the AI engine directly
- An on-chip event fabric chains camera capture, inference, and Ethernet egress with no processor involvement
- A watchdog reboot ladder recovers the chip unattended
- A/B redundant boot images in external flash
I/O architecture
- Every pin is multiplexed; the interface set is validated as complete whole-chip pin configurations
- AFPIO is a deterministic programmable I/O engine that implements additional interfaces in software; candidate applications include MIL-STD-1553 and USB full-speed
- An always-live console UART stays available in every configuration
Verification
- The full non-AI system is rehearsed on FPGA against real devices (cards, PHYs, camera sensors) before design freeze
- Interface interoperability on hardware is an entry condition to design freeze
Ordering
AF-X1 is in development. Request a quote to preorder or register interest in the first production run.
Evaluation hardware for AF-X1
Specifications are preliminary and subject to change. Orders are subject to export screening.