ArrayFoldIn design
AF-X2
10-100 TOPS of radiation-tolerant AI compute, hardened by process and by architecture.
The production flagship: multicore RISC-V processing and an AI engine sized from 10 to 100 TOPS on a substrate that resists radiation at the transistor level. Priced like a terrestrial edge-AI module.
Applications
Use it when a mission needs processing and AI acceleration in one radiation-tolerant part.
- Imaging constellations that process and act on data in orbit
- Autonomous drones and defense platforms that need serious AI in harsh environments
- Real-time sensor fusion across optical, radar, and RF payloads
- Scaling from a single flight computer to multi-chip AI clusters
At a glance
- Throughput
- 10-100 TOPS
- Efficiency
- 10+ TOPS/W (compute fabric)
- Clustering
- Scale past one chip
- vs AF-X1
- 100×+ throughput
Specifications
Scaling from AF-X1
- Clock
- 10×+ faster (projected)
- AI throughput
- 100×+ (projected)
- Efficiency
- 50×+ per watt (projected)
Same architecture on a production process. The multipliers are conservative.
An order of magnitude, everywhere.
The same design on a production process moves every number at once.
Compute
- Processors
- RV32 / RV64GCB, multicore, multithreaded
- AI engine
- Scaled-up ArrayFold compute fabric, 10-100 TOPS
- Sizing
- The range is set by customer demand, one design
- Clock
- 10× AF-X1 (projected)
Multicore RISC-V, real AI.
Application-class cores beside a compute fabric sized for onboard inference.
Memory
- External DRAM
- LPDDR4 (planned)
- On-chip SRAM
- ECC-protected with hardware scrubbing
Model capacity, finally.
LPDDR4 holds models far beyond on-chip SRAM capacity.
Clustering
- Fabric
- Multi-chip Ethernet with hardware sync
- Scale
- Single flight computer → N-chip AI cluster
- Heritage
- Cluster configuration proven first on AF-X1
The headline feature: compute scales by adding chips.
Need more? Add a chip.
The architecture assumes clustering from the start.
Interfaces
- Carried from AF-X1
- Ethernet · camera · SD · SpaceWire · CAN · AFPIO
- Additions
- Defined with early customers
Proven on AF-X1 first.
The interface set carries straight over from the first-generation part.
Plan
- Status
- In design
- First silicon
- Targeting 2027
- Package / pins
- Pending
In design now.
Early partners shape the first production run.
Radiation
Hard at the transistor. Hardened in the logic.
AF-X2 is built on FD-SOI: every transistor sits on an insulating layer that blocks most of the charge a particle strike deposits, so upsets are orders of magnitude rarer than in standard silicon before any correction runs. The triple modular redundancy, ECC, and memory scrubbing built into the part then catch what little gets through. Process hardness and architectural hardening stack.
TID and single-event test results will be published here as characterization completes.
Technical detail
Why the process matters
- FD-SOI transistors sit on an insulating layer that sharply limits the charge a particle strike can collect, cutting single-event upsets at the device level
- That process-level resistance stacks with the architectural hardening (TMR, ECC, scrubbing) built into the part
- The result is rad-hard-class behavior without rad-hard-class pricing
Measured so far
- Compute-fabric tiles already close timing at 10× AF-X1's clock in physical design, at milliwatt-scale dynamic power per tile
- Compute-fabric efficiency is tracking past 10 TOPS/W before system overheads
- These are physical-design measurements; silicon characterization data will replace them as hardware comes back
One design, two settings
- AF-X1 and AF-X2 are built from the same family components; AF-X1's silicon derisks the production design
- Cluster-capable: multiple chips link over Ethernet with hardware sync, scaling compute past a single part
Ordering
AF-X2 is the production flagship, now in design. Talk to us about preorders, early access, or partnering on the first run.
Specifications are preliminary and subject to change. Orders are subject to export screening.