Design infrastructure

The tools behind our chips.

ArrayFold builds its own design infrastructure: the workflow that turns a concept into silicon, the system of record that makes every result reproducible, and the standard every block is built to. It was built from the lessons of our first three tapeouts, and every current program runs on it. We eat our own dog food. (We also just really like dogs.)

Concept to numbers, fast.

A heavily automated workflow drives the full design flow. A new block goes from concept to first area, power, and timing numbers quickly, and iterating on those numbers is the default way of working.

Full synthesis and physical-design runs launch from one command
Every iteration returns hard area, power, and timing numbers
The same flow is running our current tapeout programs

One source of trust.

Underneath the flow sits a build system made for silicon. Every source file, constraint, and tool run is content-tracked, so any result can be reproduced exactly, months later, to the bit. Blocks declare area and timing budgets up front, and whole-chip fit is checked continuously, from the first week of a project.

Content-addressed history: every release is a snapshot that rebuilds bit-for-bit
Budgets are first-class: a block that outgrows its floorplan fails early and loudly
Whole-chip area and timing roll up automatically as the design moves

Reports that reach the wire.

Every run digests the raw mass of tool output into something a person can use. A deep scrape engine gathers, correlates, and bundles what matters, then rolls it up into a one-screen view of the design's health. Every number on that screen can be followed back down to its source. This is the report you always wanted your flow to write.

Power broken down to the line of code that burns it
Worst timing paths traced to the exact register, line, and block that own them
High-level views built from full-depth data, so a deep dive never hits a dead end
The evidence ships with the result: one run, one bundle, full traceability

Packaged, versioned, delivered.

Components live in a catalog: grouped, referenced in seconds, versioned, and packaged. A customer delivery is a pinned release with everything attached, including datasheets generated straight from backend extraction, so the documentation always matches the silicon.

Formal properties and UVM verification on every component
Registers defined once, generated everywhere: hardware, software, documentation
Radiation standards (TMR, ECC, scrubbing tiers) applied at design time and checked at release
Datasheets produced from backend extraction in minutes
Integration pulls pinned versions straight from the catalog

Availability

It starts as a conversation.

This is the flow we run every day, and what's written here is the surface. If you'd rather start a silicon program on proven infrastructure than build your own, we're open to licensing the flow with limited support. Tell us what you're building and we'll talk specifics.

Get in touch

Descriptions are intentionally high level. Nothing here is a contractual commitment or binding offer.